1. Field of the Invention
The present invention relates to a main memory control apparatus capable of realizing high-speed access to a main memory unit in a computer system.
2. Description of the Related Art
Some CPU's include cache memories storing part of the contents stored in a main memory unit, aiming at high-speed access to the main memory unit. In such a CPU, consistency or sameness of data between the cache memory and the main memory unit is maintained by a snooping function that monitors access to the main memory unit from DMA (Direct Memory Access) enable devices other than the CPU.
Some of CPU's including cache memories, however, have no snooping function. Particularly, built-in CPU's which are becoming commonly used in commercial applications incorporate cache memories for improvement of performance, but often have no snooping function for cost reduction. In those CPU's having no snooping function, consistency of stored data between a cache memory and a main memory unit is secured by software.
More specifically, CPU's can be classified into two types; i.e., performance-directed CPU's intended for application to workstations and high-level personal computers, and built-in CPU's intended for application to home game machines, electronic notebooks, etc. In general, performance-directed CPU's each have a snooping function that monitors access to a main memory unit from other CPU's or DMA enable devices, taking into account its application to a system wherein a plurality of CPU's accessing to a common memory are employed to improve performance.
The provision of the snooping function ensures consistency of data between a cache memory incorporated in the CPU and a main memory unit.
On the other hand, built-in CPU's are designed with an emphasis placed on cost performance, because apparatus and equipment utilizing such built-in CPU's are relatively inexpensive. Accordingly, those CPU's incorporate cache memories for improvement of performance, but many of them have no snooping function for cost reduction. Because of versatility in applications, the built-in CPU's occupy a great proportion in the total number of CPU's brought to the market.
In the CPU's incorporating cache memories but having no snooping function, as mentioned above, consistency of data between a cache memory and a main memory unit is secured by software. The following two methods are known so far for achieving it.
(1) Any cache memory is not employed, or a storage area of the main memory unit, which is accessed by DMA enable devices other than the CPU, is allocated to an address area from which data cannot be loaded into the cache memory in the CPU.
(2) A storage area which is accessed by DMA enable devices is allocated to an address area from which data can be loaded into the cache memory in the CPU. But if data in a main storage area which is accessed by the DMA enable devices exits in the cache memory at the DMA start-up, the data in the cache memory is invalidated.
However, the above method (1) is disadvantageous in that since CPU access to all the area of the main memory unit or the area thereof which is accessed by DMA enable devices is made directly to the main memory unit, an access time is longer than that required to make access to the cache memory.
Also, in the above method (2), it is probable that each time write access to the main memory unit is made at the DMA start-up, the contents of the cache memory are invalidated. This results is disadvantages of reducing utilization of the cache memory, lowering a cache hit ratio, and prolonging an average access time of the CPU to the main memory unit.